1. Field of the Invention
The present invention relates to a circuit and method for selectively enabling and disabling a split differential amplifier. More particularly, the present invention relates to a circuit and method for combining the functions of signal amplifying, buffering, and output enabling in a memory device by use of split bias enabling.
2. Description of the Prior Art
Circuits and techniques for communicating the contents of a solid state memory to other devices are well known. Such circuits receive a differential input, indicative of memory cell contents at an associated memory location, and produce a corresponding logic level output signal. A memory select or output enable/inhibit feature is typically included with such circuits. Accordingly, an output signal is produced only when required and as selected.
FIG. 1 shows a prior art differential applifier circuit 10, which consists of transistors Q1-Q4 and resistors R1 and R2. A logic high or low output signal is produced at transistor Q9; output enable/inhibit is controlled by transistors Q5-Q8.
In operation, if the memory cell contents to be transferred by circuit 10 are a logic high, a logic high signal IN+ is present at the base of transistor Q1 and a logic low signal In- is present at the base of transistor Q4. As a result, a current I.sub.D is steered through resistor R1 and thereafter through each of transistors Q1 and Q3. Current I.sub.D is split at the collectors of transistors Q1 and Q3. A current I.sub.D /2 flows through each of transistors Q1 and Q3 and, thereafter, through transistors Q7 and Q8, respectively.
No voltage drop is developed across resistor R2 as a result of steering current I.sub.D through transistors Q1 and Q3. The voltage is coupled to the base of transistor Q9, turning transistor Q9 on, and producing a logic high output signal at the emitter of transistor Q9.
If the memory contents transferred by circuit 10 are a logic low, a logic low input signal is present at the base of transistor Q1, and a logic high signal is present at the base of transistor Q4. As a result, current I.sub.D is steered through resistor R2 and thereafter through each of transistors Q2 and Q4; current I.sub.D /2 flows through each of transistors Q2 and Q4 and thereafter, through transistors Q7 and Q8, respectively. The voltage drop developed across resistor R2 and coupled to the base of transistor Q9 turns transistor Q9 off because current I.sub.D is now steered through resistor R2 and transistors Q2 and Q4. Therefore, a logic low output signal is produced at the emitter of transistor Q9.
A BIAS 1 signal, present at the base of transistors Q2, Q3, and Q5, sets a voltage level relative to which input signal IN+ must be more positive and relative to which input signal IN- must be more negative if circuit 10 is to produce a logic high output signal at the emitter of transistor Q9. BIAS 1 signal also sets the voltage level relative to which input signal IN+ must be more negative and relative to which input signal IN- must be more positive if circuit 10 is to produce a logic low output at the emitter of transistor Q9.
A second BIAS signal--BIAS 2--is coupled to the base of transistors Q7 and Q8 to establish an output enable voltage level. An output enable signal OE is coupled to the base of transistor Q6. Circuit 10 is operated when output signal OE is a logic low relative to the BIAS 2 signal. When output enable signal OE is a logic high relative to the BIAS 2 signal, transistor Q6 conducts and steers current I.sub.D through transistors Q5 and Q6 through resistor R2 producing a voltage drop across resistor R2. As a result, a logic low output signal is produced at the emitter of transistor Q9, without regard to logic input signals IN+ and IN-.
When the circuit is enabled, differential amplifier pairs consisting of transistors Q1 and Q2, and Q3 and Q4 are operative as follows:
______________________________________ Reading a "1" Reading a "0" ______________________________________ IN+ (base Q1) high relative low relative to Bias 1 to Bias 1 IN(-) (base Q4) low relative high relative to Bias 1 to Bias 1 Q1 On Off Q2 Off On Q3 On Off Q4 Off On I thru R.sub.2 .0. .about.I.sub.D ______________________________________
When disabled transistors Q7 and Q8 are off and transistor Q6 is on. The transistor Q1, Q2 and transistor Q3, Q4 differential amplifiers are not operative as follows:
______________________________________ Disabled Enabled ______________________________________ Q1 inoperative depends on Q2 no emitter logic state at Q3 current input IN+ IN- Q4 Q7, Q8 are off (see above) Q5 On Off Q6 On Off Q7 Off On Q8 Off On ______________________________________
One disadvantage of such prior art circuits is the need to provide a current path through transistors Q7 and Q8. Such transistors must be, of necessity, large in size to steer current I.sub.D (which may be on the order of 6 milliamperes). Such large transistors slow circuit response time by increasing circuit parasitic capacitance. Precise current steering also is inhibited by transistors Q7 and Q8, unless identical matched transistors are used to balance the transistor's steering of current I.sub.D.
The additional functional elements required by prior art enabling circuits increase both space and power requirements, while substantially slowing circuit response time. These limitations are particularly noticeable in high speed electronic devices, such as solid state memory circuits.